1. Field of the Invention
The present invention relates generally to computer systems, and more particularly, to a method and apparatus for providing a cache memory controller which facilitates the writing and reading of data from TAG memory.
2. Description of the Related Art
Recent developments in computer technology have included the widespread implementation of a direct mapped cache memory in small computers so as to improve system performance (speed). The use of a small, high speed cache in a computer system permits the use of relatively slow but inexpensive DRAM for the large main memory space. Cache memory is essentially a small, fast memory implemented on the CPU bus, in addition to a full but slower main memory on the system bus. A cache memory utilizes specialized hardware to assure that currently used parts of main memory are copied into the cache memory, and that data addressed in cache memory is still identical to the data in the corresponding locations of main memory before presenting such data as valid data on the data bus.
In general, a direct mapped cache memory comprises a high speed data RAM and a parallel high speed TAG RAM. Each RAM address in the data cache is the same as the low-order bits of the corresponding main memory address to which the entry corresponds, the high-order portion of the main memory address being stored in the TAG RAM as TAG data. The TAG RAM typically also contains a "valid" bit corresponding to each entry, indicating whether the TAG and data in that cache memory entry are valid.
When a CPU requests data from memory, the address of the data in main memory is put out on the address bus. The lower-order portion of the address is supplied as an address to both the cache data and the cache TAG RAMs. The TAG data for the selected cache entry is compared with the high-order portion of the CPU's address and, if it matches, then a "cache hit" is indicated and the data from the cache data RAM is output to the data bus. If the TAG data does not match the high-order portion of the CPU's address, or if the TAG data is invalid, then a "cache miss" is indicated, and the data is fetched from main memory in a normal main memory fetch sequence. When fetched, the data and address portions are also placed in the cache memory for potential future use, overwriting the previous entry at the corresponding cache memory address.
In existing PC AT-compatible computers, there is no way to directly read or write information in the cache TAG RAM. In the typical PC AT-compatible computer, the data pins of the TAG RAM are permanently coupled to receive input from the high-order address leads of the local bus, and are permanently coupled to provide output to a TAG match comparator. Cache TAG entries have no corresponding address in the main memory or I/O address space. For diagnostic purposes, however, it would be desirable to be able to write any desired data to a selected TAG RAM entry, and also to read the data currently in a TAG RAM entry.
U.S. Pat. No. 5,287,481 discloses one solution to this problem by providing cache control circuitry which selects the data to be written to TAG RAM from two or more sources. One of the sources is the CPU address bus and the other is a register in the chipset which may be written to an entry in the TAG RAM by writing the information to the chipset register and then selecting the cache control mode which writes the information from the register into the TAG RAM on the next main memory read access. The low-order address bits for the read access address the TAG RAM, and an additional cache control mode is provided in which the information read from a TAG entry addressed in a read access is written to the chipset register and made available for reading by the CPU. An additional mode may be selected in which the address of a noncacheable secondary memory block is selected for writing to the cache TAG RAM at the address specified on the CPU address lines during a read access to main memory, which invalidates the corresponding cache data line entry.
Thus, the present invention provides an alternate solution to the problems in existing cache memories as discussed above.